EGEC 542 - VLSI Testing and Design for Testability (3)

Fault model, equivalence and dominance; combinational and sequential circuit test generation ; design for testability (DFT); test compression; memory testing and diagnosis; boundary scan; testing analog circuits; mixed-signal testing strategies; logic and mixed signal built-in self test (BIST).

Prerequisite: EGEC 441 or graduate standing.

Graduate-level

Typically Offered: Periodically